Company: Rain Neuromorphics Inc.
Location: San Francisco, CA
Position Type: Full Time
Experience: See below for details
Education: See below for details
Verify dsgn of key SoC subsystems & RTL blocks & full SoC functionality. Verify arithmetic of deep learning operations on custom silicon blocks. MS deg in EE, Comp Eng or rltd + rltd exp. Salary - $133,162. CV, Attn: A. Santalo, Rain Neuromorphics, 660 York St, SF, CA 94110.
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Company: ProteinSimple
Location: San Jose, CA
Position Type: Full Time
Experience: See below
Education: See below
Senior Manager, Manufacturing, ProteinSimple, San Jose, CA. Req. Bachelor’s deg. in Mechanical Engr. or closely rel. engr. fld. & 8 yrs. as Manufacturing Engineer or rel. occupation in Mfg. Operations w/in biotech industry; or Master’s & 6 yrs. exp. Must possess at min. 5 yrs. in each of the following: computer aid design; Root Cause Analysis incl. FMEA; 5S problem solving; new product introduction mgmt.; supply chain mgmt.; & lean mfg. For confidential consideration, apply at https://www.bio-techne.com/about/careers. No agencies or phone calls. Show more »
Location: San Jose, CA
Position Type: Full Time
Experience: See below
Education: See below
Senior Manager, Manufacturing, ProteinSimple, San Jose, CA. Req. Bachelor’s deg. in Mechanical Engr. or closely rel. engr. fld. & 8 yrs. as Manufacturing Engineer or rel. occupation in Mfg. Operations w/in biotech industry; or Master’s & 6 yrs. exp. Must possess at min. 5 yrs. in each of the following: computer aid design; Root Cause Analysis incl. FMEA; 5S problem solving; new product introduction mgmt.; supply chain mgmt.; & lean mfg. For confidential consideration, apply at https://www.bio-techne.com/about/careers. No agencies or phone calls. Show more »
Refcode: #IPCSFC00145541
Company: Lime Bikes
Location: San Francisco, CA
Position Type: Full Time
Experience: See below
Education: See below
Must have BS degree in Management Info. Systems, Comp. Sci or related or foreign equiv. and min. 2 yrs. exp. using Python & wkging w/ data analysis. Sal: $181K-$186k/yr. Send res: resumes@li.me & ref: “LDE24BS” Show more »
Location: San Francisco, CA
Position Type: Full Time
Experience: See below
Education: See below
Must have BS degree in Management Info. Systems, Comp. Sci or related or foreign equiv. and min. 2 yrs. exp. using Python & wkging w/ data analysis. Sal: $181K-$186k/yr. Send res: resumes@li.me & ref: “LDE24BS” Show more »
Refcode: #IPCSFC00143771
Company: Kepler Computing
Location: San Jose, CA
Position Type: Full Time
Experience: See below for details
Education: See below for details
Salary Range: $178,006 to $250,000 Rate of Pay: Employer will pay or exceed the PW as determined by DOL Location: San Jose, CA (Telewrk Permitd) Send Resume to: ta@keplercompute.com Duties: ASIC Engr will: design & characterize circuits on lead process nodes & integrate into chip subsys w/ indust-std place & rte/timing anlys tools; doc specs; perf prototype constructn & checkout; modify & eval designs; devlp sols to probs utilizing formal edu & prof judgmnt; & work cross-funct’ly w/ sys team to integrate ASIC soln results into final prod. Edu/Exp: MS or eq in EE, Elec Mag, ME, Control Sys or rel + 3 yrs exp; or BS or eq in EE, Elec mag, ME, Control Sys or rel + 5 yrs exp: Wrk in ASIC dev cycle creating high-lvl prod specs while wrkg directly w/ ASIC Engr Lead; Wrk w/ SoC (sys on a chip) des, impln & intg w/ ASIC Engr Lead; Design micro-arch & RTL using Sys Verilog RTL to meet pwr targts, perf targts & area targts as defined by prod specs; Deploy var Place & Rte (PnR), Back End & Front End tools: Synopsys ICC/ICC2, Sysnopsys Primetime & Primetime SI, Cadence Birtuoso, Conformal, Verplex, Innologic & Stratus; Prog/script langs: Perl, Python, Tel, CIC++, Shell Script, SKILL Prog & Verilog; Use ind tools for RTL synth, PnR, timing anlys, & layout verif to des, impl, & test ASIC des; Collab w/ Prod Sys team & Prod Leads on des & intg of completed ASIC design into lrgr sys construct; RTL des using Verilog, SysVerilog, VCS,Verdi; Des partitioning, synth, placement, rte & time closure for ASICs' using Cadence/Synopsys tools; & Writing TCL/Python/Perl script to reduce des iterations & improve des prod. Show more »
Location: San Jose, CA
Position Type: Full Time
Experience: See below for details
Education: See below for details
Salary Range: $178,006 to $250,000 Rate of Pay: Employer will pay or exceed the PW as determined by DOL Location: San Jose, CA (Telewrk Permitd) Send Resume to: ta@keplercompute.com Duties: ASIC Engr will: design & characterize circuits on lead process nodes & integrate into chip subsys w/ indust-std place & rte/timing anlys tools; doc specs; perf prototype constructn & checkout; modify & eval designs; devlp sols to probs utilizing formal edu & prof judgmnt; & work cross-funct’ly w/ sys team to integrate ASIC soln results into final prod. Edu/Exp: MS or eq in EE, Elec Mag, ME, Control Sys or rel + 3 yrs exp; or BS or eq in EE, Elec mag, ME, Control Sys or rel + 5 yrs exp: Wrk in ASIC dev cycle creating high-lvl prod specs while wrkg directly w/ ASIC Engr Lead; Wrk w/ SoC (sys on a chip) des, impln & intg w/ ASIC Engr Lead; Design micro-arch & RTL using Sys Verilog RTL to meet pwr targts, perf targts & area targts as defined by prod specs; Deploy var Place & Rte (PnR), Back End & Front End tools: Synopsys ICC/ICC2, Sysnopsys Primetime & Primetime SI, Cadence Birtuoso, Conformal, Verplex, Innologic & Stratus; Prog/script langs: Perl, Python, Tel, CIC++, Shell Script, SKILL Prog & Verilog; Use ind tools for RTL synth, PnR, timing anlys, & layout verif to des, impl, & test ASIC des; Collab w/ Prod Sys team & Prod Leads on des & intg of completed ASIC design into lrgr sys construct; RTL des using Verilog, SysVerilog, VCS,Verdi; Des partitioning, synth, placement, rte & time closure for ASICs' using Cadence/Synopsys tools; & Writing TCL/Python/Perl script to reduce des iterations & improve des prod. Show more »
Refcode: #IPCSFC00144791
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